Aspects of the present invention relate generally to the field of system development and test, and more specifically to verification of circuit designs.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries, and may be facilitated with an electronic design automation (EDA) tool that allows a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit.
After or during the design and creation of an IC layout, validation, emulation, and debugging operations are often performed on the IC layout using a set of testing, analysis and validation tools. However, such operations for a large and complicated circuit design often require a substantial amount of resources, including both memory and processing power. Designers often have to request access to special resources in order to complete the validation, emulation, and debugging. Such hardware based verification platforms (HBVP) are more powerful than a typical workstation, are often expensive and therefore tend to be shared among teams of designers, and are often used around the clock by various design teams. This limited access to necessary resources often severely affects design schedules.
Accordingly, there is a need in the art for a system that facilitates the debugging by providing comprehensive offline debugging capability, reducing complete reliance on shared testing resources.